Performance analysis of operational transconductance amplifier at 180nm technology

This paper presents tutorial on performance analysis for the two-stage CMOS operational transconductance amplifier in conventional gate driven mode. Both the theoretical calculations and computer aided simulation analysis have been given in detail. Designs have been carried out using TSMC 180nm CMOS process. Schematic simulations have been carried out using `Pyxis Schematic' and simulations have been done using simulator `Eldo', version 11.2 of Mentor Graphics. Initially DC analysis is performed to find region of operation of all the transistors. Results shows that all the transistors are perfectly operating in saturation region. Further AC analysis demonstrates that Gain of the Op Amp is 75 dB, Phase Margin is 53.8°, & Unity Gain Bandwidth is 30.5MHz Also CMMR is 77.8dB & input referred noise voltage is 0.0fV/√Hz. From transient analysis, slew rate is obtained to be 0.37V/μs, settling time as 472ns. The output swings up to 1.25V and the op-amp dissipates power of 536.5μW under supply voltage of 1.8V. In order to have low power op-amp, supply voltage is scaled to 1.5V & further to 1.2V. The comparative analysis of the results shows that significant saving in power, 18% and 35% respectively, can be obtained without compromising for phase margin & slew rate and little compromise in few characteristics like gain, UGB, and CMRR with supply voltage scaling.