3-D Edge Termination Design and ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ -BV Model of A 700-V Triple RESURF LDMOS With N-Type Top Layer

3-D edge termination design and analytic model for specific on-resistance (R
_ON
,sp) versus breakdown voltage (BV) of a 700-V triple reduced surface field lateral double-diffused MOSFET (LDMOS) with n-type top layer are presented in this paper. To eliminate the premature avalanche breakdown induced by the electric field crowding and the local charge imbalance in the transition region of the source-centered edge termination structure, 3-D numerical simulations and experiments are performed to investigate two crucial parameters L
₁
and L
₂
in the layout of the transition region. It is observed that optimal electric field distribution is obtained and breakdown positions are transferred to the active region at L
₁
= 30 μm and L
₂
= 1 μm. On the other hand, an analytic model is developed to describe the relation between R
_ON
,sp and BV, which is obtained as RON,sp = 5.93 × 10
^-6
× 22(T/298)1.7 × BV
²
and theoretically verifies that the fabricated device has achieved optimized R
_ON
,sp and BV. Compared with our previous paper, the LDMOS experimentally demonstrated improved performance with R
_ON
,sp of 86.49 mQ · cm
²
and BV of 805 V, which is leading performance for the 700-V applications in published data.