A high-efficiency good linearity 21 to 26.5 GHz fully integrated power amplifier using 0.18 μm CMOS technology

This paper presents the design and implementation of a 21-26.5 GHz broadband, two stages CMOS power amplifier (PA) for quasi-millimeter wave band wireless communication systems. The proposed PA is designed using staggered tuning method [1], which is employed for the first time in quasi-millimeter wave band. Moreover, source and load-pull simulation, in addition to, impedance analysis are employed to optimize the input, output, and inter-stage impedance matching circuits for maximum power added efficiency (PAE) and better linearity. The measurement results on a chip fabricated using 0.18 μm CMOS technology shows a power gain of 10.2 ± 0.8 dB, a maximum PAE and output gain compression point (Pout1dB) of 10.5 dBm and 18 %, respectively, at 24 GHz while consuming 42 mW only. In addition, the PA achieved excellent low measured group delay variations of 75 ± 22 ps.