A 24-mW 65-nm CMOS TI-Flash ADC for multi-standard serial-link receivers

A 4-channel 4-bit flash analog-to-digital converter is presented with 10Gbps sampling speed and a figure-of-merit of 182 fJ/conversion-step. It uses a conventional clocking scheme, along with a modified sample-and-hold and comparator chain circuits that reduce the overall ADC power consumption, and enhances both the resolution and accuracy without the need for any digital calibration. The ADC is designed using 65-nm CMOS technology and tested for input signals up to 5 GHz with ENOB of 3.7 bits. The reported DNL and INL are 0.42 LSB. The ADC channels are programmable to provide optimum power consumption for multi-standard serial-link applications. The latency for each sub-ADC output is about one and half clock cycle.