Improving mains current quality for three-phase three-switch buck-type PWM rectifiers

Modulation schemes for three-phase three-switch buck-type pulsewidth modulation rectifiers where the switching state of one bridge leg is clamped within a π 3-wide interval of the mains period guarantee minimum switching losses as well as minimum input filter capacitor voltage ripple and minimum dc current ripple. However, as shown in this paper by a detailed analysis of the time behavior of the input filter capacitor voltages within a pulse period such modulation schemes are characterized by the occurrence of sliding intersections of the filter capacitor voltages which causes input current distortion. An advanced modulation scheme is proposed which prevents the input current distortion and allows it to maintain the optimum performance of conventional modulation schemes. The theoretical considerations are finally verified by measurements on a 5-kW hardware prototype.