Energy efficient bootstrapped CMOS inverter for ultra-low power applications

This paper describes an energy efficient boot-strapped CMOS inverter for ultra-low power applications. The proposed design is achieved by internally boosting the gate voltage of the transistors (via the charge pumping technique), and the operating region is shifted from the sub-threshold to a higher region, enhancing performance and improving tolerance to PVT variations. Despite the proposed bootstrapped driver operates with a sub-threshold power supply it uses fewer transistors engaging in this region by utilizing two stages. The first stage is a normal driver with PMOS and NMOS transistors that are driven by the enhancing voltage circuit (stage 2) which generates voltage levels theoretically between -V
_DD
for pulling up to 2V
_dd
for pulling down. Our analysis shows that the proposed implementation achieves around 20% reduction in energy consumption compared to conventional designs under a supply voltage of 0.15V V
_DD
.