Design of high speed CRC algorithm for ethernet on FPGA using reduced lookup table algorithm

This paper describes the design and development of modified CRC algorithm for the hardware implementation on FPGA to meet the speed constraint for Ethernet, using the reduced lookup table algorithm. This algorithm can be applied for any length of data, by processing it in a block of 16 bytes at a time. The last block may have less than 16 bytes. To process an input block of 16 bytes, the algorithm first forms an optimized table of pre-calculated CRC. Corresponding to the input data, lookup from this table is done and the results from the table lookup are combined by XOR operations to form the final CRC of the input data. The Ethernet data whose CRC needs to be calculated is processed in blocks of 128 bits at clock frequency of 312.5 MHz to achieve a throughput of 40Gbps. The entire design is functionally verified using ModelSim SE Plus 6.3g. Applications in Internet of Things and Machine-to-Machine require real time big data platforms and Artificial Intelligence platforms, where there is high demand for lower latency and high speed network infrastructure. To create such a reliable network infrastructure at high speeds, a hardware accelerated CRC error detection needs to be used.