FPGA Based DDR3 Applications in a Multichannel Channelization Data Cache

In the FPGA engineering implementation of digital receiver, to complete a full probability signal capture, doing multichannel channelization with high sampling rate of analog to digital converter data is a highly effective processing. But its caching large amounts of data need to use external memory SDRAM. In this paper, with large bandwidth and high rate characteristics of DRR3, By designing a special writing and reading management system for caching multichannel channelization data, resolved the requirements of small resource utilization and high speed data throughput in the engineering implementation for the FPGA.