Energy efficient logic gates using subthreshold adiabatic logic

Adiabatic logic circuits offer significant reduction in power dissipation when compared with static CMOS. Subthreshold adiabatic logic is a new energy recovery logic. In this paper the efficiency of all logic gates with this novel logic is compared with conventional counterpart. The performance of each logic gate circuit and energy consumption is studied in terms of different technologies, supply voltages and operating frequencies. The proposed circuits are designed and simulated using CADENCE technology. The simulation results shows that the subthreshold adiabatic logic saves more than 90% of power compared to static CMOS.