Fast-lock phase-locked loop with adaptive controller in 0.18-μm CMOS

In this paper, a developed theoretical model of phase-locked loops (PLL) frequency synthesizer is presented. The proposed model aims to improve the control accuracy and reducing the lock time. A conventional phase-locked loop is designed using a backstepping control algorithm to operate at 2.2GHz using 0.18μm CMOS technology. The lock time was reduced by adding backstepping technology in addition with the traditional second order loop filter and the tuning variables of the backstepping control in order to ensure the control accuracy. The simulation results indicate that the performance of backstepping PLL control are superior and are more effective than conventional PLL. The lock time for the conventional PLL was 2.1 μs. By adding backstepping controller the lock time become 1μs showing the improvement and reduction of the lock time by 53% over the conventional PLL.