Impacts of Leakage-Biasing Failure-Mode Identification in the Transmission-Line Pulse Testing for Low-/High-Voltage MOSFET Components

The effects of leakage-biased voltage (V
_LB
) levels are investigated in this paper, which are set for failure-mode identification on the final fault diagnostic measurement in transmission line pulse (TLP) testing. To identify the effect on electrostatic discharge (ESD) robustness, three types of MOSFET components were employed; namely, low-voltage n-channel MOSFET (LVnMOS) (5 V/0.6 μm), high-voltage n-channel MOSFET (HVnMOS), and high-voltage p-channel MOSFET (HVpMOS) (12 V/1.8 μm) devices under test (DUTs), respectively. After a series of systematic TLP measurements, this study determined that the set V
_LB
level substantially influenced the failure mode identification and I
_t2
value decision on the LVnMOS and HVnMOS DUTs, but its effect on the HVpMOS DUT was extremely weak. According to the secondary breakdown current (I
_t2
) values, the error caused by a maximum V
_LB
level was up to 55.6% in the LVnMOS DUT, 81% in the HVnMOS DUT, and only 3.38% in the HVpMOS DUT. Consequently, this engendered a considerable deviation in most data derived from testing DUTs through TLP compared with those derived from a human-body model (HBM). Hence, to ensure a high correlation between values measured through TLP testing and an HBM for the same DUTs, the V
_LB
level should be considered during TLP testing. The lack of correlation is demonstrated to be due to a moderate soft and hard failure during TLP measurement especially for the LVnMOS and HVnMOS samples. Therefore, to obtain accurate I
_t2
values for DUTs, the V
_LB
level for the failuremode identification in TLP testing should be within a low-biasing range (such as kept V
_LB
≤ 5 V).