Testability for resistive open defects by electrical interconnect test of 3D ICs without boundary scan flip flops

A three-dimensional integrated circuit is fabricated by stacking multiple dies. A resistive open defect may occur at interconnects between the dies by a void and a crack during fabrication process. We have proposed an electrical test method for an IC made of dies in which boundary scan flip flops are not embedded. In this paper, testability of the test method for resistive open defects is examined by Spice simulation. The results show that a resistive open defect whose resistance is greater than 150Ω is able to be detected at a test speed of 500kHz.