Warpage simulation and experiment for panel level fan-out package

Nowadays, fan-out package is regarded as one of the latest and most potential technologies due to lower cost, smaller and thinner form factor, better electrical performance, and better thermal performance. Compared with traditional flip chip ball grid array (FCBGA), fan-out technology eliminates many process steps such as substrate, wafer bumping, flip chip reflow, flux cleaning, underfill, etc. However, warpage induced by molding is a critical issue due to the mismatch of the coefficient of thermal expansion (CTE) among the constituent materials, which is needed to be solved for successful subsequent process of the fan-out package. In this study, warpage issue of panel level fan-out package induced by molding based on "Die Last" process is investigated. Warpage simulation and experiment are carried out by finite element method (FEM) and shadow moire, respectively. A novel warpage simulation method is presented for large area panel or wafer level simulation. In order to verify the accuracy and precision of the simulation method, a molded panel sample without dies is fabricated, and warpage experiment is carried out by shadow moire. Simulation and experimental result are compared with good agreement.