Adiabatic logic: An alternative approach to low power application circuits

Today's major concerns in designing VLSI circuits have been the amount of power dissipated by these circuits. The Adiabatic logic technique is becoming an answer to the problem of power dissipation. The term `Adiabatic' refers to the change of state that occurs without the loss or gain of heat. The adiabatic switching technique reduces the power dissipation during switching events. But, adiabatic circuits highly depend upon power clock and parameter variations. In this paper mux, one bit sum and carry adder are designed and simulated on cadence Virtuoso using 180nm technology. In an analysis PFAL is compared with conventional CMOS logic on the basis of frequency and supply voltage. The proposed technique shows the reduction of power dissipation as compared to the conventional CMOS design style. And results analysis accomplishes that adiabatic logic can be used for the implementation of relatively large, complex circuits that dissipate less energy than conventional CMOS designs.