Design of PLL using improved performance ring VCO

Phase Locked Loop (PLL) is basic building block of several communication systems to achieve synchronization. In this paper the PLL is designed using improved performance ring VCO with 0.18 μm CMOS technology and supply voltage of 3 V. The proposed ring VCO which has higher tuning range is used for implementation of PLL in order of GHz frequency range. The phase frequency detector (PFD) is another part of PLL which is designed using multiplexer which gives more accurate results. The low pass filter which is connected with charge pump is designed using switched capacitor technique in which resistor is replaced by transistors and capacitor by which the overall area of the circuit is reduced. The designed PLL has a power consumption of approximately 28 mW at the operating frequency of 2.5 GHz.