A Monte Carlo simulation method to predict large-density NAND product memory window from small-array test element group (TEG) verified on a 3D NAND Flash test chip

We developed a Monte Carlo simulation method to accurately predict the large-density NAND flash product memory window based on several device parameters collected in the small-array test element group (TEG). The required parameters include the ISPP slope, intrinsic Vt distribution sigma, program noise, random telegraph noise (RTN), and various interference ratios. All these parameters can be collected from the wafer acceptance test (WAT) of a small-array TEG. The simulation methodology is to randomly generate a Vt distribution ensemble that resembles the product memory cell. Programming simulation of each memory cell considers the programming distribution and various fluctuation factors during ISPP programming and verification. Experimental data of a fabricated 3D NAND test chip are compared with the simulation results, and show excellent consistency. This novel methodology not only provides memory product window from device parameters of TEG, but also emulates various MLC programming algorithms to optimize the product-level memory window.