Improvement of short-term frequency stability of the Chip Scale Atomic Clock

Utilization of the Chip Scale Atomic Clock (CSAC) today gives great potential for wide range of strategic systems requiring superior long-term frequency stability. Compared to CSAC, an OCXO has many drawbacks, e.g. it has larger long-term frequency instabilities (aging rate), longer warm-up time and higher power consumption. On the other hand, the main disadvantage of the CSAC is the higher phase noise. In this paper we describe a method of improvement of the CSAC SA.45s short-term frequency stability (phase-noise) using an external OCXO (MTI 230-0827) syntonized to the CSAC. In the low power mode, the CSAC SA.45s consumes less than 20 mW of power; however it operates as simple TCXO and over a full operating temperature range, the frequency stability is limited to ±1 ppm. In the last part of the paper we introduce combined low power clock system that can achieve frequency stability ±0.01 ppm over a wide temperature range, while consuming similar power.