Board-Level Reliability Performance of Discrete Power Packages

Board-level thermal cycling reliability performance of two buckets of discrete power packages is evaluated by both Finite Element Analysis (FEA) and an actual test. One bucket consists of smaller size packages and the other consists of bigger size packages. The testing condition follows the established industry standard, IPC-9701, with a temperature range of 0°C ~ 100°C. In FEA modeling, the fatigue life of the board solder joint for gate connection is calculated using both the Darveaux method and modified Coffin-Manson method. In actual board-level thermal cycling tests for a typical power PQFN package, real-time monitoring of the sample units was conducted and no failure was observed until 6000 cycles. By comparing the actual reliability testing data, both the Darveaux method and modified Coffin-Manson method are valid and reliable for the PQFN package board-level solder joint reliability assessment. FEA simulation results show that the power discrete packages with the bigger size are more robust than those with the smaller size. Another observation is that power discrete packages with extended pins out from the package body could improve the board-level thermal cycling reliability performance. The board-level solder joint profile is modeled for a rectangular shape pin of the PQFN package using the Surface Evolver tool, which resulted in a comparable profile as the actual samples. Based on the evaluation from both the FEA modeling and actual testing, more robust power discrete packages could be designed and manufactured.