2.5D X-Clock Tree Construction Based on Stacked-Layer Combination of Multivoltage Islands

This paper presents an algorithm of 2.5D X-clock tree construction for the stack-layer combination of multivoltage islands. Double via insertion is also considered for via-effect avoidance and reliability. The algorithm can reduces the complexity of 3D clock tree construction of a stacked-layer chip. A clock network is first be partitioned into the number of voltage islands distributed on each layer, such as L-type and T-type, and the X-clock tree is constructed for each voltage island. Then, we integrate these X-clock trees based on a well-defined connection each layer by inserting level shifters and TSVs for minimizing the power with the best trade off in power and delay. Experimental results show that our approach can save up to 10.04% and 35.18% effectively on average in power and delay, respectively.