Performance analysis of low power 6T SRAM cell in 180nm and 90nm

The memories are more and more used as an embedded element rather as a separate block. Being used as a macro, its user has nothing to change or optimize. So, the design of memory needs to address all the issues specially to optimize the rigorous area and power requirements. This paper discusses the issues in design of SRAM memory cell for low power applications. 6T architecture SRAM cell is taken as a reference model which is designed using 180nm technology. The power, area and speed is estimated. The cell is designed using 90nm technology and is used in 8K memory. The performances of the memory in 180nm and 90 nm technology is compared and analyzed for area, power and speed. The design is simulated using cadence virtuoso for schematic entry and layout. For comparison microwind is used for analysis and performance comparison. The results clearly indicate that as we migrate from 180nm to 90nm technology power reduces and speed increases on a single SRAM bitcell. The results have been verified using BSIM3 model files, simulated at 27 degree centigrade setting appropriate voltages.