Targeting hardware trojans in mixed-signal circuits for security

The proliferation of third-party silicon manufacturing has increased the vulnerability of integrated circuits to malicious insertion of hardware for the purpose of leaking secret information or even rendering the circuits useless while deployed in the field. A key goal is to detect the presence of such circuits before they are activated for subversive reasons. One way to achieve this is to detect the presence of parasitic loads on internal nodes of a victim circuit. However, such detection becomes difficult in the presence of normal process variations of the silicon manufacturing process itself. In this work, we show how high-resolution detection of parasitic loads on internal circuit nodes can be achieved using a combination of test stimulus design and design-for-Trojan detection techniques. We illustrate our ideas on digital as well as analog/mixed-signal circuits and point to directions for future research.