III–V-on-Si Photonic Crystal Nanocavity Laser Technology for Optical Static Random Access Memories

Heterogeneous integration of III-V semiconductors on silicon has gained considerable momentum fueled by the need to implement fully functional photonic devices and circuits in a CMOS compatible platform. In this communication, we report on a III-V photonic crystal (PhC) nanocavity, heterogeneously integrated on a silicon-on-insulator platform, to form a PhC nanocavity laser capable of exhibiting two elementary static random access memory (SRAM) cell functions individually, namely switching and latching operations under a high-speed, bit-level regime. As such, the PhC nanocavity laser is examined as a generic logic functions building block, suitable toward multiGb/s energy-efficient, optical SRAM cells with minimal device footprint. The proposed device occupies a total area of only 6.2 μm
²
, rendering in this way the demonstrated memory element the smallest among the integrated optical memories presented so far. Bit-level SRAM cell operation requires two elementary functions: the access gate (AG) switching function and set-reset flip-flop (SR-FF) latching function. At first, AG switching operation is evaluated through successful wavelength conversion at 10 Gb/s, revealing a power penalty of 1 dB at 10
^-9
BER and a switching energy of only 4.8 fJ/bit. Then, fully functional SR-FF memory operation is successfully demonstrated, exhibiting error-free operation with negative power penalty at 5 Gb/s and switching energies of 6.4 fJ/bit. FF operation at higher speeds of 10 Gb/s with reduced switching energy levels of 3.2 fJ/bit is also experimentally investigated. Both logic operations were demonstrated separately with the same PhC nanocavity laser device exhibiting <;50 ps switching times and evaluated under real-type data traffic patterns, raising expectations for beyond 20 Gb/s capabilities toward implementing energy-efficient, ultracompact and high-speed true optical SRAM setups for Datacom applications.