Virtual impedance method of the Power hardware-in-the-loop simulation to improve its stability and accuracy

This paper uses virtual impedance method to improve the stability and accuracy of the Power hardware-in-the-loop (PHIL), which mainly deals with the errors introduce by the interface equipment. A PHIL system, which consists of a real-time simulator (RTS), interface equipment (IE) and a hardware under test (HUT), has been discussed and its impedance model has been analyzed. Based on the analysis, a virtual impedance method that uses the compensated impedance (implemented in software) is proposed more stable and accurate simulation performance can be obtained by using the virtual impedance method. The validity of the proposed method is verified through the off-line simulation and PHIL experiments.