Low-power, high-performance 64-bit CMOS priority encoder using static-dynamic parallel architecture

The performance of priority encoder circuits is usually limited by the delay associated with the propagation of the priority token, however, proper design in the architectural level can reduce the delay stages to the order of O(log n). Furthermore, power dissipation and area pose an increasingly important concern in modern circuit design, thus the development of suitable techniques is essential. This paper introduces a new 64-bit priority encoder based in a static-dynamic parallel priority lookahead architecture and a newly designed 4-bit PE cell. Compared to conventional works, it achieves up to 34% reduction in transistors, 80% reduction in power and 53% improvement in performance.