A Bottom-Source Single-Gate Vertical Channel (BS-SGVC) 3D NAND Flash Architecture and Studies of Bottom Source Engineering

Vertical channel (VC) 3D NAND Flash may be categorized into two types of channel formation: (1) "U-turn" string, where both BL and source are connected at top thus channel current flows in a U-turn way; (2) "Bottom source", where source is connected at the bottom thus channel current flows only in one way. For the single-gate vertical channel (SGVC) 3D NAND architecture [1], it is also possible to develop a bottom source structure. The detailed array decoding method is illustrated. In this work, the challenges of bottom source processing and thin poly channel formation are extensively studied. It is found that the two-step poly formation and the bottom recess control are two key factors governing the device initial performance. In general, the two-step poly formation with additional poly spacer etching technique seems to cause degradation of both the poly mobility and device subthreshold slope. Sufficient thermal annealing is needed to recover the damage. Moreover, the bottom connection needs an elegant recess control for better read current as well as bottom ground-select transistor (GSL) device optimizations.