Voltage over-scaling in sequential circuits for approximate computing

Approximate Computing has attracted much interest over the last decade, as it promises to substantially increase the energy efficiency of a variety of applications. Its core idea is to trade off the accuracy of an application with its power consumption. It hereby relies on the ability of many applications and the human perception to accept or not to notice minor quality degradations of a computed result. A reduction of the precision of an application, and hence the power consumption, can be reached by many techniques and on many levels of abstraction. This work focuses on the approximation of sequential integrated circuits by aggressively scaling the supply voltage of the logic gates of a circuit, hence accepting timing violations. Compared to previous work, the approach presented in this work is a generic approach that can be automatically applied to any digital circuit. We are achieving this by scaling each timing path of a timing endpoint individually. In order to do so, we are first estimating at which supply voltage which timing path is failing. Then we are estimating the resulting error probability, for which we developed a simple and fast method that allows us to conservatively assess it. Applied to an exemplary benchmark circuit, the presented approach allowed us to save up to 27% of the power, without having a major degradation of the quality. Furthermore, we were able to demonstrate, using the presented methodology, that only very few over-scaled voltage domains can be sufficient to substantially decrease the power consumption.