Device-Circuit Cosimulation for Energy Efficiency in Sub-10-nm Gate Length Logic and Memory

Sub-10-nm gate length devices are expected to have severe short channel effects along with new leakage mechanisms, such as direct source-to-drain tunneling (DSDT). In this paper, in order to improve the leakage and to obtain the highest performance/stability in such deeply scaled devices, we perform device–circuit cosimulation for sub-10-nm gate length to optimize devices for logic and memory. For that purpose, double-gate MOSFETs with sub-10-nm gate length are optimized using symmetric/asymmetric gate-to-source/drain underlaps to improve the ON-state current to the OFF-state current ratio and the intrinsic gate delay. Using resulting device characteristics, the effectiveness of supply gating to improve standby leakage in the circuits is studied. We show that supply gating is effective in reducing DSDT current, as well as thermionic leakage current. Also, various SRAM designs are explored to improve stability and leakage in sub-10-nm gate length bit-cells. The analysis shows that 6T SRAM bit-cells with asymmetrically underlapped devices can provide improvement in read stability over symmetric 6T bit-cells, as well as traditional 6T bit-cells. However, the need for higher stability in the sub-10-nm gate length regime due to parameter variation would require us to investigate other bit-cell configurations. Our analysis on 1R/1W differential 8T SRAM bit-cells show that significant increase in read/write stability as well as improvement in write time, and leakage can be achieved compared with the optimized 6T SRAM bit-cells.