A double-end sourced multi-chip improved wire-bonded SiC MOSFET power module design

This paper proposes an improved wire-bonded design with a unique double-end sourced (DES) structure for multi-chip paralleled silicon carbide (SiC) power modules. The new structure adopts two pairs of DC bus-bars to source the power module from the two ends, not only shortens the equivalent power loops but also provides a symmetrical structure for the paralleled devices. The proposed design achieved a minimized power-loop inductance of 7.2 nH. In addition, the design improved current sharing among the paralleled devices. A 1200 V, 60 A SiC metal-oxide-semiconductor field-effecttransistor (MOSFET) half-bridge module (3 devices in parallel) is fabricated and tested for verification. Improved performances are observed in both switching and continuous operation. A converter level design is also presented to accommodate this unique module structure.