The impact of PLL loop bandwidth on Frequency Synthesizer'S performances for LTE/ LTE-Advanced mobile communications

The major goal of this article consists on the optimization of lock time and reference spurs in PLL Frequency Synthesizer for LTE/LTE Advanced mobile communications. The most important objective in the design of a PLL frequency synthesizer is to achieve a trade-off between reference sidebands and switching speed. This paper demonstrates that these characteristics largely depend on the synthesizer's loop filter. The loop filter must be designed for the correct balance between reference spurs and lock time that the system requires. Generally, the narrower the loop bandwidth the lower the reference spurs but the longer the lock time.