A low-voltage level shifter based on double-gate MOSFET

Energy consumption is a major concern in nanoscale integrated circuits. Aggressive low-power design to maximize the battery life is a significant challenge. Multi-VDD design is an effective approach for decreasing the power consumption especially in battery-powered digital VLSI designs. Hence, in these designs, voltage level shifters (LSs) as an interface between these different voltage islands are required. This paper presents a new single-supply level shifter (SSLS) based on independent double-gate (IDG) SOI MOSFET. In the proposed technique, the back gate of transistors is utilized for tuning the threshold voltage (Vt) of transistors in order to convert low-voltage input signals and decrease static power consumption. Simulation results conducted based on Berkeley Independent Multi-Gate model at 32nm technology node demonstrate a qualified performance of the proposed multi-Vt design compared to the other common and most efficient LS circuits.