An FPGA Memory Hierarchy for High-level Synthesized OpenCL Kernels

In this paper, we propose an FPGA memory hierarchy based on the OpenCL memory model. The memory hierarchy allows application-specific memory optimizations during design compilation using information provided in OpenCL kernels. With the proposed memory hierarchy, FPGA application developers can focus on their designs in OpenCL kernel codes, and their designs can be synthesized into FPGA hardware via high-level synthesis. In the FPGA hardware, our proposed memory hierarchy handles memory management efficiently regardless of application types, and consequently, developers are free from designing application-specific memory hierarchies.