Test methodology for the geostar correlator

Proposed approaches to the NRC Earth Science Decadal Survey's Precipitation, All-Weather Temperature, and Humidity (PATH) mission involving synthetic aperture arrays require massively parallel, high speed correlators implemented on a geostationary satellite platform. We present testing methodology for a coarse digital correlator chip using a low-power ASIC architecture. The chip was designed in the Electrical Engineering and Computer Science Department of the University of Michigan. These tests precede the integration of the chip into a Geostationary Synthetic Thinned Aperture Array (GeoSTAR) instrument prototype in development at NASA's Jet Propulsion Laboratory.