An Efficient Adaptive Method of Software-Based Self Test Generation for RISC Processors

The contribution presents automatic software-based self (SBST) test generation for processors as a basic blocks of current complex systems on chip and embedded systems. Processors testing can be extended by functional tests or using various application programs. Such types of tests are serving as additional tests to structural testing or as tests used in verification. Functional tests (programs) are generated over an instruction set architecture and processor model description. A metric for quality evaluation of the software-based tests is obviously provided by code coverage of a processor model. A new functional test generation method, presented in the paper, is based on VHDL models of processors and genetic algorithms with using various evolutionary strategies. In addition a new method for starting population of the used genetic algorithms has been proposed. Functionality and effectiveness of the developed methods were evaluated in the implemented system AGenMIX over one type of RISC processor.