Implementation of Math PRR and LED Processing Using Xilinx PlanAhead

Runtime Partial Reconfiguration (PR) of FPGA is an attractive feature which offers countless benefits across multiple industries. Xilinx has supported PR for many generation of devices. PR dynamically modified hardware portion of the device function downloading full and partial bit streams. The modules which were used during the experiments have been presynthesized and the netlist files were stored in synth directory. The data directory carried the ucf, busmacro and additional netlist files. In this paper the authors reconfigure some specific region of the FPGA with a new functionality at run time while the remaining areas remain static during this time. The complexities during the runtime can be simplified by a tool called PLANAHEAD which was introduced by XILINX that is able to implement during runtime reconfigurable systems for all VIRTEX field programmable gate array (FPGAs). PLANAHEAD is the first graphical environment for partial reconfiguration which gives the flexibility for reducing the board space, change a design in the field and also reduces the power consumption.