A wearable human activity recognition system on a chip

The availability of cheap wearable motion and biometric sensors has favoured the research on wearable human activity recognition (HAR) systems. However, a HAR system comprehends many complex signal processing stages that usually require some computationally demanding operations which can hardly be directly performed in an embedded system. Modern FPGA technologies and the system-on-chip (SoC) approach open the door to the implementation of complex single-chip signal processing systems to produce tiny, wearable and autonomous embedded HAR systems. However, compared to a pure embedded software approach, the potentially higher performance-to-power ratio of FPGAs can only be exploited in very demanding applications and by a careful design of the implemented system. In this work we describe a first step in the consecution of an FPGA-based completely autonomous singlechip HAR system which can be adapted and optimized to the user with no need of external computing means neither of human intervention. The system includes all stages in a HAR process, i.e., signal segmentation, signal processing for feature extraction, input space dimensionality reduction (feature selection), and activity estimation by means of a neural classifier. A physical activity recognition example is used as a reference design to evaluate the performance of the system and to draw conclusions on the potential benefits of using FPGAs in future wearable HAR applications.