A Two-Dimensional Gate Threshold Voltage Model for a Heterojunction SOI-Tunnel FET With Oxide/Source Overlap

A two-dimensional (2D) analytical gate threshold voltage model for a heterojunction silicon-on-insulator tunnel field-effect transistor structure with gate oxide overlap is developed. The infinite series method, with suitable boundary conditions, is used to solve the 2D Poisson's equation for surface potential. The surface potential is used to develop the expression for the proposed analytical threshold voltage in closed form. Developed threshold voltage is verified for different gate length, drain voltage, oxide thickness, and gate dielectric materials against Synopsys Technology Computer-Aided Design numerical simulation results and found to predict the simulated results accurately.