Design of high performance 8 bit Vedic Multiplier using compressor

This paper proposes the design of high speed Vedic Multiplier using the compressor which is based on ancient Indian Vedic mathematics that has improved the performance of multiplier. As the technology advent the Multiplier require high speed, low power and small area. Vedic mathematics, a system of ancient Indian mathematics, which has a unique technique of solutions based on only 16 sutras. In this paper we introduce a new architecture of Vedic multiplier by using 4:2 compressors and 7:2 compressors for addition that increase the speed of Multiplier and reduce the area 2% than Urdhwa-Tiryakbhyam Multiplier. The 7:2 compressors are made of 5:2 compressors and two full adders. The design was performed on a Xilinx Spartan 3 series of FPGA and the timing and area of the design, on the same have been calculated.