A Case Study of Multiprocessor Bugs Found Using RIS Generators and Memory Usage Techniques

Random Instruction Sequence (RIS) Generators are widely used for functional verification of processors. In the case of multiprocessor systems, these RIS tools can be used to generate instructions that act upon data shared between the multiple processors in the system. In addition to the random instruction sequences, addition of semi-directed functional sequences and deterministic instruction patterns in the tool -- orthogonal to the randomly generated instructions increase the chances of reaching the desired corner cases faster. Using carefully crafted address reuse and virtual memory mapping data inconsistency issues and arbitration bugs in the processors can be hit faster. This paper presents a case study of two bugs which were found in cache coherent multiprocessor systems using a RIS tool, and semi-directed sequences.