Hybrid single electron transistor based low power consuming 4-bit parallel adder/subtractor circuit in 65 nanometer technology

Hybridization between CMOS logic and single electron transistor has already revolutionized our present nano technological aspects. Ultra low power consumption as well as ultra dense circuit formation is now possible with the help of mutual integration between the two mentioned above. These benefits have drawn the attraction of the future researchers in this hybrid SET-CMOS technology for future nano-scale low power VLSI design. In this paper, we have designed a room temperature operable 4-bit adder/subtractor circuit in hybrid SET-CMOS logic with considerably low power consumption. Power-delay product has also been calculated numerically and graphically. XOR gates are used as controlled inverter for the selection of add or subtract operation. All the simulations are performed in Tanner environment and for the simulation purpose two separate model files are used. MIB model for SET operation and BSIM4.6.1 for the operation of PMOS. It is notable that the hybrid structure provides far better performance in respect to the conventional MOSFET structure.