Low-power/low-swing domino CMOS logic

A new low-power domino CMOS logic is introduced. Its power characteristics are based on a low voltage swing technique. The output inverter of the domino gate is modified in order to reduce its output voltage swing. This results in dynamic power dissipation saving up to 36% and improvement in the power-delay product. A technique for creating changeable values of the voltage swing is used achieving various trade-off between power savings and speed. Experimental results clearly show the validity of the proposed technique for low-power operation.