Real-time implementation for reduced-complexity LDPC decoder in satellite communication

In this paper, it has proposed a real-time implementation of low-density paritycheck (LDPC) decoder with less complexity used for satellite communication on FPGA platform. By adopting a (2048, 4096) irregular quasi-cyclic (QC) LDPC code, the proposed partly parallel decoding structure balances the complexity between the check node unit (CNU) and the variable node unit (VNU) based on min-sum (MS) algorithm, thereby achieving less Slice resources and superior clock performance. Moreover, as a lookup table (LUT) is utilized in this paper to search the node message stored in timeshare memory unit, it is simple to reuse and save large amount of storage resources. The implementation results on Xilinx FPGA chip illustrate that, compared with conventional structure, the proposed scheme can achieve at last 28.6% and 8% cost reduction in RAM and Slice respectively. The clock frequency is also increased to 280MHz without decoding performance deterioration and convergence speed reduction.