Cross-layer system resilience at affordable power

In this paper, we address the challenge of achieving very high energy efficiency, while meeting target levels of performance and resilience to transient errors. We focus mainly at the processor chip level, while keeping in mind two ends of the system spectrum: (a) low power, real-time constrained embedded systems; and (b) extreme-scale high performance systems (or supercomputers). We advocate and illustrate the use of cross-layer resilience optimization as a general solution strategy.