Single-Event Cluster Multibit Upsets Due to Localized Latch-Up in a 90 nm COTS SRAM Containing SEL Mitigation Design

We report a study on a COTS 90 nm low-power SRAM chip, which is immune to single-event latch-up due to its on-chip latch-up suppression circuit. However, under heavy-ion as well as proton irradiation test, the chip exhibits cluster flips, i.e. flipping of tens of bits due to a single particle strike. We attribute the cluster flips to localized latch-up events that can affect a segment of 32 × 64 bits, which is supported by TCAD simulations. We suggest to further scrutinize the latch-up suppression design, due to its apparent inability to prevent localized latch-ups.