Keynote: Si based tunnel-field effect transistors for energy efficient electronics

A great obstacle for ultralow power MOSFETs functioning at very low voltages is their physical limit of the inverse subthreshold swing of 60 mV/dec at 300K. Quantum mechanical tunneling of carriers from the source into the channel in Tunnel-FETs overcomes in principle this hurdle. However, the fabrication of powerful complementary Tunnel-FETs with high Ion/Ioff ratios and steep slopes is still a great challenge. Nevertheless, Tunnel-FETs are considered as the most promising concept as steep slope devices. In this contribution an overview will be given mainly on Si based Tunnel-FETs. Results of planar and nanowire TFETs with Si, strained Si and Silicon-Germanium will be shown. Particular emphasis will be placed on the device performance improvement by formation of the steep tunnel-junction and the improved device electrostatics defined by the gate stack and the geometry of the device. We have developed a novel process to produce complementary TFETs and first TFET inverters. Strained Si nanowire TFETs show on currents well above 10 μA/μm at VDS= 0.5 V and n-TFETs reach a minimum slope of 30 mV/dec. Inverter voltage transfer curves and their time response will be presented. The TFET inverters show sharp transitions and high gain even at very small voltages, VDD = 0.2V, indicating their potential for energy efficient electronics.