A generalized low power and lower jitter charge pump PLL

In this paper, design a fast locking time and low jitter PLL based on Self-Biased technology. The PLL designs achieve process technology independent, broad frequency range and low input tracking jitter. The loop bandwidth will track operating frequency, therefore, sets no constraint on the operating frequency range. Self-biasing avoids the necessity for external biasing, by generating all of the internal bias voltages and currents from each other so that the bias levels are completely determined by the operating conditions. The PLL is implemented in SMIC 0.13µm MS/RF 1P8M CMOS technology. The design is simulated by a software called Cadance spectre, and the layout is shown. Simulation results show that this circuit can achieve a very wide tuning range is 500MHz to 2 GHz and the phase noise is −91.08dBc/Hz@1MHz, the jitter RMS value is 4.9ps in central frequency at 1.25GHz and the die area of the PLL is 250um × 420um.The power dissipation of the PLL core is only 10mW at a 1.2V supply.