Optically interconnected integrated circuits to solve the CMOS interconnect bottleneck

The performance of future generation data processing systems will be set by interconnect limitations rather than by IC performance. The main reason for this expected I/O-bottleneck is the projected increase in CMOS IC-complexity, in terms of chip size, number of I/O pads and clock frequency. Problems inherently associated with closely packed electrical interconnections (such as cross-talk, signal distortion EMI) will lead to bandwidth limitations, in turn resulting in a mismatch between silicon processing capabilities and interconnect performance. Optical I/O over the entire chip area is pursued as a solution to these interconnection problems in the European Community funded ESPRIT project OIIC ("Optically Interconnected Integrated Circuits"). In this approach, data transfer from the whole chip area is facilitated through two dimensional arrays (array pitch: 250 /spl mu/m) of optical channels, consisting of opto-electronic components flip-chip mounted on CMOS circuitry and aligned to passive optical pathways. Data rate objectives are 0.5-1 Gb/s per channel. As a principal choice in this project, a 2D array of small diameter (125 /spl mu/m) Plastic Optical Fibres is used as a flexible transmission medium. The large numerical aperture of this fibre (typically NA=0.5) and its flexibility allow for compact assembly (and hence low head room modules) and relatively coarse alignment.