21.3 A 2GHz 130mW direct-digital frequency synthesizer with a nonlinear DAC in 55nm CMOS

Direct-digital frequency synthesizers (DDFSs) have been employed in many frequency-agile communication systems because of their wide bandwidth, fine frequency resolution, and fast frequency-hopping characteristics. Recent developments in DDFSs are towards enhancing performances through reduction of both complexity and power consumption [1-3]. The segmented nonlinear DAC (NLDAC) structures in [1,2] require additional coarse phase information for fine amplitude decoding with a complex decoder. Moreover, the quarter-sine-wave technique incorporated into the segmented NLDACs in [1,2] degrades spectral purity due to the need of the MSB shift DAC that introduces additional offset. Another scheme in [3] reduces complexity and power consumption by replacing the digital-based phase-to-amplitude converter with an analog-based converter, resulting in limited spectral purity. Unlike previous schemes, this work presents comprehensive enhancements in all key areas of a DDFS, the pipelined phase accumulator (PACC), digital decoder, and NLDAC as shown in Fig. 21.3.1. First, the low-power PACC with multi-level momentarily activated bias (M
²
AB) is presented to reduce power dissipation. Second, the coarse phase-based consecutive fine-amplitude grouping (C
²
FAG) scheme reduces the hardware complexity and the power consumption in digital decoder circuits. Third, the mixed-wave conversion topology (MCT) in the NLDAC improves the output spectral purity.