Groove structure for stress releasing around TSV

Through silicon via (TSV) is one of the most significant techniques in microelectronic packaging. In 3 dimensional integrated circuit (3D IC), TSV brings great performance improvement and high density device integration. Meanwhile, the usage of copper in TSV causes serious thermal stress issue, which considerably affects the device performance and reliability. This paper proposed a unique structure to release TSV-induced stress. Numerical simulation was used to study the stress distribution around the TSV and optimize the geometric parameters, including the depth, width and position of the proposed stress-releasing groove.