Nonbinary LDPC Decoder Design and Implementation on FPGA Platform

Emerging standards for wireless communications in the 60GHz band, such as WiGig, IEEE 802.11ad, and IEEE 802.15.3c, require throughputs between 1.5 and 6 Gb/s and use rate adaptive Nonbinary Low Density Parity Check (NB-LDPC) codes as the main form of forward error correction. State-of-the art flexible NB-LDPC decoders cannot simultaneously achieve the high throughput mandated by these standards and the low power needed for mobile applications. Although various kinds of low complexity iterative decoding algorithms have been proposed, the FPGA implementation of NB-LDPC decoders still remains a big challenge due to its high complexity and long latency. Moreover, Prototype architecture of the NB-LDPC codes has been implemented by writing Hardware Description Language (VHDL) code and targeted to a Xilinx Spartan-3E XC3S500E FPGA chip. In this brief, a highly efficient check node processing scheme, which the processing delay greatly reduced, is proposed for Min-max decoding algorithm. Thereafter, an efficient check node unit (CNU) can be designed. Compared with previous works, the latency of the CNU could be reduced to less than 52%. In addition, a decoder for a (620, 310) NB-LDPC code is designed to demonstrate the efficiency of the presented techniques.