A Distributed BIST Scheme for NoC-Based Memory Cores

This paper proposes a distributed Memory Built- In-Self Test (MBIST) architecture employing a hybrid technique for testing heterogeneous memory cores interconnected using NoC. In the proposed architecture, the memory cores are placed in different groups based on distance and timing constraints. Each group has a dedicated BIST controller which performs parallel March test on all the cores in a group while the groups are tested in a pipeline. The paper also proposes a test schedule for the proposed architecture to keep the test power within the power budget. Experiments performed on ITC'02 benchmark circuit confirms that our proposed test schedule performs a more power constrained test as compared to dedicated BIST technique. Moreover, experimental results indicate real estate benefits for the proposed distributed BIST architecture in comparison to other reported techniques.